Digital Logic Simulator

Complete Credit to Sebastian Lague for the orginial simulation, and AOx0 for merging the pull requests.

Feat: Set Group Size by sagitarious12, 4, 8, and 16 bit bus wires by t4ccer, menu to rename and elete custom chips by gml16, and improvments to the edit menu by Tigralt, with miscellaneous changes by me (Turnip1234).

WebGL builds are not supported on mobile devices.